This invention relates to digital timing circuitry, and it relates, more particularly, to a synchronization circuit which operates while the digital system clock is running to skip a clock pulse to achieve synchronization.
In time-division multiplexed digital communication systems, an operation known as demultiplexing requires synchronization in order to divide a serial data stream properly into a number of channels. Various techniques have been devised to achieve and maintain synchronization through out digital communication systems. For example, one technique called pulse stuffing is often used to insure that synchronization is maintained by providing an appropriate signal format in serial transmission systems. Another somewhat conversely related technique involves achieving synchronization by removing clock pulses from a series of clock pulses in response to a command or control signal. This technique is useful in synchronous digital systems wherein a machine cycle is composed of multiple clock cycles. All parts of the system must begin their machine cycles on the same cycle in order for the system to function synchronously. A circuit known as a pulse swallower is able to achieve synchronization for one part of a system while the system is running by swallowing clock pulses entering that part of the system until synchronization occurs.
For a variety of reasons, a trend has developed wherein digital systems operate at increasingly faster and higher rates. Conventional pulse swallowers are limited due to their circuit configurations to a maximum operating frequency of one over six .tau. (1/6 .tau.) where .tau. corresponds to the average delay interval associated with the operation of a typically loaded gate. In terms of the duration of a clock cycle, the period of the clock cycle must be no shorter than six .tau.. Although integrated circuit technologies have developed with less delay to reduce the value of .tau., the previous frequency constraint of conventional pulse swallowers still presents a degradation in the maximum frequency of operation of digital communication systems.